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Recent questions tagged verilog

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verilog - What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?

I tried to figure out the inferred latch and why it is needed internally, but I couldn't find any resources with enough detail. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - What is `+:` and `-:`?

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: ... -: width_expr] up_vect [lsb_base_expr -: width_expr] Question&Answers:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - I don't understand this define macro with replication

I have SystemVerilog code in which replication is used that I don't understand. Please be thorough with ... questions/65836185/i-dont-understand-this-define-macro-with-replication...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - $fgetc SystemVerilog function doesn't read from stdin

In the following testbench module for_loop; int c; initial begin $display("Write Here!"); c = $fgetc( ... com/questions/65841430/fgetc-systemverilog-function-doesnt-read-from-stdin...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Why are "if..else" statements not encouraged within systemverilog assertion property?

I am writing an assertion check for the following structure Basically, I want to check that output is ... are-if-else-statements-not-encouraged-within-systemverilog-assertion-prop...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - For loop with binary numbers

I want to use a for loop in Verilog to get from binary 0000000 to 0011111. I have a problem with the ... :https://stackoverflow.com/questions/65927030/for-loop-with-binary-numbers...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 4 bit register with enable and asynchronous reset

I am modelling a 4 bit register with enable and asynchronous reset . The register has three one bit input ... /questions/65713489/4-bit-register-with-enable-and-asynchronous-reset...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Arbitrary Counter only displaying zeros

I have to make an arbitrary counter for a determined sequence, and after making the transition ... stackoverflow.com/questions/65643542/arbitrary-counter-only-displaying-zeros...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

I want to create a very compact parallel to serial shift register. (我想创建一个非常紧凑的并行串行移位寄存器 ) I have manually designed a ... 我尝试在TinyFPGA.BX上编译代码 ) ask by E. Timotei translate from so...

asked Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

I want to create a very compact parallel to serial shift register. (我想创建一个非常紧凑的并行串行移位寄存器 ) I have manually designed a ... 我尝试在TinyFPGA.BX上编译代码 ) ask by E. Timotei translate from so...

asked Feb 21, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Writing random data to a RAM in a testbench

I am working with RAM in Verilog, and I need to implement a test bench where I will confirm the correct ... always @ (instraddr) begin instrrd=mem[instraddr]; end endmodule...

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Passing packed data to a task to be compared with an unpacked data array for uvm constraints

I'm trying to create a task for a UVM sequence that takes a packed data input and uses it for a constraint on ... in a basic setting it appears what I originally wrote would work....

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Parameterizing a SystemVerilog interface for optional array of a port element

I would like to fill in the correct signal declarations and the modport declarations so that my interface and ... a single element for their particular instantiation and code....

asked Feb 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Functional Coverage - bin that collects all values that are not collected in other bins

ipv6_hdr__f_next_header_cp: coverpoint this.ipv6_hdr.ipv6_f_next_header iff (this.has_ipv6_header){ bins ipsec_33 = {'h33}; bins ... way of making the default an active bin?...

asked Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Functional Coverage - bin that collects all values that are not collected in other bins

ipv6_hdr__f_next_header_cp: coverpoint this.ipv6_hdr.ipv6_f_next_header iff (this.has_ipv6_header){ bins ipsec_33 = {'h33}; bins ... way of making the default an active bin?...

asked Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - How can I automatically scale a $display column width?

I want to $display strings in a column like in a fixed-width table. However, I don't know what the maximum column ... need. How can I automatically scale the width of the $display?...

asked Jan 25, 2021 in Technique[技术] by 深蓝 (71.8m points)

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3.8k views

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verilog - Does this SystemVerilog code have the wrong sequence of code?

I wrote the following SystemVerilog code inside always_comb: // State transitions SW2_REP: begin casex (mani) 1'b0: next = ... its value to zero. Note: my clock is 11 cycles...

asked Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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3.9k views

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verilog - Does this SystemVerilog code have the wrong sequence of code?

I wrote the following SystemVerilog code inside always_comb: // State transitions SW2_REP: begin casex (mani) 1'b0: next = ... its value to zero. Note: my clock is 11 cycles...

asked Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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